Accelerating seismic computations using customized number representations on FPGAs

A stream Compiler (ASC)

We use our object-oriented ASC FPGA programming tool to develop a range of different solutions. ASC, A Stream Compiler, was developed following research at Stanford University and Bell Labs, and is now commercialized by Maxeler Technologies. ASC enables the use of FPGAs as highly parallel stream processors. ASC is a C-like programming environment for FPGAs. ASC code makes use of C++ syntax and ASC semantics which allow the user to program on the architecture-level, the arithmetic-level and the gate-level. In contrast to other methodologies, ASC provides the productivity of high-level hardware design tools and the performance of low-level optimized hardware design. On the arithmetic level, PAM-Blox II provides an interface for custom arithmetic optimization. On the higher level, ASC provides types and operators to enable research on custom data representation and arithmetic. ASC hardware types are HWint, HWfix and HWfloat. Utilizing the data-types we build libraries such as a function evaluation library or develop special circuits to solve particular computational problems such as graph algorithms. A simple example of an ASC description for a stream architecture that doubles the input and adds '55' looks as follows:

%\lstset{language=ASC}
%\begin{figure}[ht]
%\begin{lstlisting}
// ASC code starts here
STREAM_START;

// Hardware Variable Declarations
HWint in(IN);
HWint out(OUT);
HWint tmp(TMP);

STREAM_LOOP(16);
tmp = (in << 1) + 55;
out = tmp;

// ASC code ends here
STREAM_END;
%\end{lstlisting}
%\caption{A simple ASC example} \label{fig:asc_example}
%\end{figure}

The ASC code segment shows HWint variables and the familiar C syntax for equations and assignments. Compiling this program with `gcc' and running it creates a net-list which can be transformed into a configuration bitstream for an FPGA.

Accelerating seismic computations using customized number representations on FPGAs