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The shot profile imaging condition has a high arithmetic density, meeting the requirements for FPGA acceleration.
The zero time part of the imaging condition (Equation 2),
which requires a summing over
all frequencies nf.
In addition each input point is going to be
used in nh cross-correlations.
Despite the high arithmetic density of the offset gather, the arithmetic capabilities of the FPGA are substantially in excess of that required so acceleration is limited by the rate at which data can be streamed across the bus from main memory to the accelerator. In this case, the performance is limited by:
| |
(3) |
where bw is the number of bits used to represent each value. This condition arises because the PCI-Express bus is symmetric, providing limited input and output bandwidth. Two arrays (S and G) containing nf data items per coordinate are sent to the FPGA and one array (I) is sent from the FPGA back to the processor, containing nh data items per coordinate. By reducing the number of bits stored for each value from 32 to 16 the performance of the operation can be doubled, with negligible degredation in the output image.
The on-chip memory requirement is , well within the capabilities of modern FPGAs for hundreds of frequencies and dozens of subsurface offsets. This allows very large datasets to be processed easily with only a small fraction stored on-chip at any one time.
Next: Results
Up: Pell and Clapp: Accelerating
Previous: FPGA Acceleration
Stanford Exploration Project
5/6/2007