next up previous [pdf]

Next: Downward continued based migration Up: Fu et al.: FPGA Previous: Introduction

Project overview

As a first step it is useful to begin by defining some FPGA terminology.

Block RAM
Small memory elements (store up to 512 single-precision floats) located within the FPGA. The Xilinx Virtex 4 FX100 FPGA contains 376. All BRAMs can be read and written in parallel and combined into larger memories, leading to very high internal bandwidth.
FIFO
First-In-First-Out Memory queue built from Block RAMs. FIFOs exploit temporal locality in data streams.
Slice
A unit of area on Xilinx FPGAs. Each slice contains 2 (on most current FPGAs) lookup tables (LUTs), the basic compute unit on an FPGA, each LUT implements any 4-input 1-output logical function. We connect LUTs to implement arithmetic and control logic.
PCI Express x8
State-of-the-art bus for FPGA acceleration. 4000MB/sec peak bandwidth.

FPGAs are Complementary metal–oxide–semiconductor (CMOS) technology-based chips containing logic which can be configured to any sequential circuit and a limited number of memory elements including RAMs and registers. The price of reconfigurability is a 10x slower dynamic clock frequency compared to modern processors. We exploit the parallelism and ability to use custom number representations to overcome the lower clock frequency and obtain a higher performance.

The long term goal of this project is to speed up key seismic imaging application by at least a factor of 10x over conventional multi-core hardware.



Subsections
next up previous [pdf]

Next: Downward continued based migration Up: Fu et al.: FPGA Previous: Introduction

2007-09-18