Accelerating seismic computations using customized number representations on FPGAs

Number Representation

Precision and range are key resources to be traded off against the performance of a computation. We looked at three different types of number representation: fixed-point, floating-point and logarithmic. Consider the case when $U_{i}$ is represented as a fixed-point number, with an integer part $I$ which is $a$ bits in length, and a fraction part $F$ which is $b$ bits in length.

$i_{a - 1}\ ...\ i_{2}\ i_{1}\ i_{0}$

$f_{0}\ f_{1}\ f_{2}\ ...\ f_{b - 1}$

The integer bit-width, which represents the dynamic range of the number, is calculated according to equation (1):

$$k \geq \lceil log_{2}(\vert max(U_{i}) - min(U_{i})\vert) \rceil$$ (1)

For the floating-point number system, let $U_{i}$ represent a floating-point number $(-1)^{S} \cdot M \cdot 2^{E}$, where $S$ is the sign bit, $M$ is the mantissa with a bit-width of $m$ bits, and $E$ is the exponent with a bit-width of $e$ bits.

$S$

$i_{0}\ i_{1}\ i_{2}\ ...\ i_{m - 1}$

$f_{e - 1}\ ...\ f_{2}\ f_{1}\ f_{0}$

The value of the mantissa $M$ is expressed as:

$$M = \sum_{i = 0}^{m - 1}{a_{i}2^{-i}}$$ (2)

where $a_{i} \in \{0, 1\}$.

It is possible to relate the bit-width $m$ of the mantissa of the node to the error when representing the mantissa by a finite bit-width $Errflt$, as follows:

$$Errflt(m) = \left\{ \begin{array}{l l} 2^{-m} \times 2^{E} & ... ...imes 2^{E} & \quad \mbox{if truncation}\\ \end{array} \right.$$

where $E$ is the value of the exponent at the node.

Since there is no standard to encode logarithmic numbers, in this report we use a fixed-point format to store the logarithmic value.

Accelerating seismic computations using customized number representations on FPGAs