Selecting the right hardware for Reverse Time Migration

Programming Difficulty

As mentioned in the above sections, the streaming architecture of FPGAs show great potential for achieving high performance for RTM. However, the difficulty in programming FPGAs has long been considered a disadvantage that prevents FPGA from becoming a general computation solution.

Firstly, the mindset for programming an FPGA is much different from the mindset of software programming. In contrast to writing a sequence of logic and mathematic operations in software programming, programming an FPGA is more like writing a description of a hardware design. The programmer needs to specify the input and output variables of each unit as well as the timing schedule between different signals. The different mindsets bring significant difficulties for common users, who are usually more into the software programming mindset, to map their designs into the FPGA's streaming architecture.

Secondly, the FPGA programming process itself is also much more complicated. In early days, FPGA programmers used to write their design using VHDL or Verilog, which are very low level hardware description languages. In recent years, people have made various efforts to develop high-level compilers for FPGA programming. Some of the emerging high-level compilers manage to hide most of the low-level details of hardware design, and enable the users to describe the hardware design using a high-level language, such as C++/Java.

void stencil_operator(input, coeff, output){
   
   output = coeff[0] * input +
            coeff[1] * (prev(input, 1) + after(input, 1) + 
                        prev(input, nx) + after(input, nx) + 
                        prev(input, nx*ny) + after(input, nx*ny)) +
            coeff[2] * (prev(input, 2) + after(input, 2) +
                        prev(input, 2*nx) + after(input, 2*nx) +
                        prev(input, 2*nx*ny) + after(input, 2*nx*ny)) +
            ......
}

The above shows an example of a high-level description for a 3D stencil operator. In this high-level description, the arithmetic operations are described using straightforward arithmetic expressions. The complicated window buffer mechanism (as described in previous sections) is described using the offset functions `prev' and `after'. In this piece of pseudo code, `prev' and `after' functions simply return the value of the variable in previous or afterwards cycles. By specifying the offset as a certain number of data items, data rows or even data slices, the compiler can automatically generate a buffer that covers all the data items needed for the current stencil operator. Therefore, the programming difficulty is significantly reduced.

Selecting the right hardware for Reverse Time Migration