next up previous [pdf]

Next: Data Compression Up: FPGAs Previous: Processing Multiple Time Steps

Bit-width Minimization

Conventional seismic processing is performed on a CPU with 32 or 64-bit precision for all operations. In certain cases, using a reduced precision produces equivalent results within acceptable tolerances. However, as CPUs do not support configurable bit-widths, reducing precision brings no benefits to performance. In contrast, FPGAs enable application-specific number representations. With hardware support for reconfigurable number format and bit-width, reduced precision can greatly decrease the area cost and I/O bandwidth of the design, thus multiplying the performance with concurrent processing cores on an FPGA.

In our previous work on exploring different bit widths in complex exponential operations Fu et al. (2008), we show that in certain parts of the calculation, fixed-point numbers with 12 bits can be applied to achieve a similar accuracy as 32-bit floating-point numbers. Similarly, for the 3D convolution in RTM algorithm, we can achieve acceptable accuracy using 24-bit fixed-point numbers instead of 32-bit floating-point numbers. The reduction in representation precision leads to significant reduction in the area cost of arithmetic operations and the bandwidth requirement between the FPGA and the outside data memory. As a result, the performance of the design gets significantly improved.


next up previous [pdf]

Next: Data Compression Up: FPGAs Previous: Processing Multiple Time Steps

2009-10-16