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Next: Acknowledgments Up: Fu et al.: FPGA Previous: Further potential speedups

Conclusions

We describe a software methodology for implementing and evaluating algorithmic performance on a FPGA. We found a 8x speedup in implementing (including transfer time) the FK step of downward continued migration on FPGA. In addition we found a 5-8x speedup in implementing a acoustic 3-D convolution kernel.


2007-09-18